Semiconductor DRAM memories conventionally include memory cell arrays, equalizer circuits, pre-charge circuits, sense amplifiers, bit lines and word lines. One commonly used structure includes twisted bit lines. FIG. 1 shows an example of a section of a simple conventional DRAM memory. The memory elements (not specifically shown) are located at the intersection of the word lines designated WL and the bit lines designed by the numbers 131 to 138. The bit lines 131 to 134 are twisted pair bit lines and the bit lines 135 to 138 are not twisted. Each pair of bit lines has an associated equalizer circuit and pre-charge circuit designated 121 to 128 and an associated sense amplifier designated 110 to 117. To improve area efficiency, each sense amplifier is used by two memory cell arrays.
The manufacturing processes for integrated circuits do not always produce perfect devices and each device must be tested after it is manufactured. Burn in testing which sometimes use elevated temperatures and elevated voltages is commonly used to insure that DRAM memories when shipped operate according to their specifications.
On commonly used burn in test creates a voltage difference between adjacent memory cells. In a memory which does not have twisted pair bit lines, this can be done by simultaneously enabling the 0, 3, 4 and 7 word lines and pre-charging the bit lines with a high voltage and then enabling the 1, 2, 5 and 6 word lines and pre-charging the bit lines with a low voltage.
With a memory that includes twisted bit lines such as that shown in FIG. 1, the test procedure described above would not result in voltage differences between all the adjacent cells. FIG. 2A illustrates the application of test voltages. FIG. 2B shows the resulting voltages on a representative number of memory cells. As indicated in FIG. 2B, the bit line BL0 intersects four high voltage cells (indicated by the circles with vertical cross-hatching) and bit line BL0B intersects four low voltage cells (indicated by the circles with horizontal cross-hatching). Thus, the sense amplifiers can sense the voltage difference between lines BL0 and BL0B. Bit lines BL1 and BL1B each intersect two high voltage cells and two low voltage cells. As a result in a memory with twisted bit lines, if all the word lines are simultaneously activaqted, there will not be an appropriate voltage between bit lines BL1 and BL1B and the test will not operate satisfactorily.
Therefore, prior art designs that address the above problem divide the word lines into groups as follows:
For the sense stress test:                WL_4k and WL_4k+3        WL_4K+1 and WL_4K+2        
For the write stress test:                WL_4K and WL_4K+2        WL_4K+1 and WL_4K+3        
Thus four test pads are required to activate the appropriate word lines for the tests.